The present disclosure relates generally to the field of semiconductor fabrication, and more particularly to the fabrication of high-performance complementary metal-oxide-semiconductor structure with III-V n-channel field effect transistors and silicon-germanium p-channel field effect transistors on insulator.
As silicon (hereinafter “Si”) complementary metal-oxide-semiconductor (hereinafter “CMOS”) technology continues to scale down its minimum critical dimension, which is the transistor gate length, it becomes increasingly difficult to enhance device switching speed due to fundamental limitations. New device engineering is indispensable in overcoming difficulties of advanced CMOS and realizing high performance large scale integrations under, for example, the 10 nm gate length regime. In addition to the improvements of gate stacks using metal gate/high k gate dielectrics and the channel electrostatic control using fully-depleted silicon-on-insulator substrates and multi-gate metal-oxide-semiconductor field-effect transistors, new channel material with enhanced carrier transport properties are needed for enhancing the performance of CMOS-based circuits and chips.
III-V n-channel field effect transistors are considered a compelling candidate for extending the device scaling limits of low-power and high-speed CMOS circuits and chips, owing to their enhanced electron transport properties compared to those of Si. Silicon-germanium p-channel field effect transistors are also considered a compelling candidate, owing to their superior hole transport properties compared to those in Si.